Modern integrated circuits (ICs) and/or circuit designs intended for implementation within an IC are often created using a hardware description language (HDL). An HDL is a computer-language that allows a designer to specify a digital system at a high level of abstraction. An HDL design is usually modular in nature. In many cases, an HDL design incorporates one or more Intellectual Properties or cores. The cores are connected together within the circuit design to function as a system. In the normal case, little time is spent designing a circuit design at the gate level.
Approximately half of the time available for system design may be devoted to HDL simulation. HDL simulation is a process that tests the functionality of an HDL design prior to implementation of that HDL design in an IC. HDL design generally includes a compile phase and a runtime phase. The compile phase elaborates the HDL design to generate executable models of the HDL design that are saved for later execution. The runtime phase executes the executable models in order to simulate the HDL design.
A typical HDL design process entails choosing the cores for inclusion in the HDL design, connecting the cores, building a testbench for testing, compiling the HDL design (which includes the testbench), and then running the HDL simulation. Any time that another core is added to the HDL design, one or more of the existing cores is changed, or the testbench is changed, the entire HDL design is compiled again. This process continues to iterate with the designer modifying the HDL design (including the testbench), compiling the entire HDL design, and performing the runtime phase for the compiled HDL design to determine whether established requirements are met.
Unfortunately, the compile phase is time consuming. The cores utilized in modern HDL designs are large in size and require significant computational resources, e.g., time and memory, to compile. Thus, significant time is spent in the design cycle waiting for the compile phase to complete in order to perform the runtime phase of HDL simulation.